1. Field
The embodiments disclosed herein relate generally to manufacturing technologies for electronic circuits and, more specifically, to a method and apparatus for insertion of filling forms within a design layout to enable elimination of jog areas within the structure.
2. Background
In order to achieve increased semiconductor manufacturing yield, physical design data is generally inserted into a semiconductor design layout, before applying an optical proximity correction (“OPC”) procedure to the integrated circuit database. The design layout is a representation of the integrated circuit and includes geometric shapes and layers that correspond to the physical structure used in actual fabrication. During the OPC procedure, the presence of small jog areas, notches, or other design errors in the design layout leads to a significant increase in data volume, reduced OPC results around the regions containing the errors, and increased difficulty in inspecting the masks of the design layout.
Typically, in an inspection process subsequent to insertion of filling forms, the design layout is subjected to a design rule checking procedure (“DRC”), which applies a collection of design rules to the layout to detect any potential design rule violations and to minimize defects in the fabrication process. In one example, one potential design rule violation relates to the encroachment of a geometric shape into the spacing mandated between the geometric shapes and layers of the design layout. Thus, any removal of jog areas and notches from the design layout should be performed with a view to achieving a DRC-clean design layout.
Several approaches have been proposed to remove the jog areas and notches from the design layout. In one such approach, the jog areas and notches are removed manually via a modification of the geometries of the design layout. However, this approach is labor-intensive and time-consuming.
Another approach involves the use of a script to insert appropriate patches to remove corresponding jog areas in the design layout. However, this approach could create a high number of circuit design rule violations, which subsequently have to be manually modified to comply with the appropriate design rules.
Thus, what is needed is a method and apparatus to insert filling forms within a design layout such that jog areas and notches present in the design layout are removed automatically in compliance with appropriate circuit design rules.